As device dimensions decrease in size, and device density increases, it becomes more and more difficult to build an efficient and reliable isolation process to separate active devices. The limits of the standard LOCOS (LOCal Oxidation of Silicon) process have motivated the search for new isolation schemes.
The conventional, non-recessed, LOCOS-type process will not be adequate much below 0.9 .mu.m active area-field pitch. This is the pitch which is suitable for the 16M DRAM, but is not suitable for the 64M DRAM generation.
Isolation for 256 Mb and greater density DRAMS, and 64 Mb and greater density SRAMS can not use standard LOCOS for isolation. Some of the problems with current isolation schemes are physical encroachment size, field oxide thinning effect, poor electrical isolation, and processes which are complicated and expensive.
One new isolation scheme is Poly Buffered LOCOS (PBL), which employs a thin polysilicon layer between the oxide and nitride films in the LOCOS stack.
PBL facilitates design rule shrinking and smaller cell size required for submicron and sub-half-micron device fabrication. This isolation scheme utilizes an oxide/poly/nitride sandwich to block oxidation of the active regions during field oxidation growth. The presence of the intermediate poly layer allows the oxide to be thinned and the nitride thickened without generating undue stress in the active regions in order to reduce encroachment during the field oxidation step.
One PBL method is referred to as ONO PBL because an oxide/nitride/oxide sandwich is used between the substrate and the polysilicon layer. See for example, U.S. Pat. No. 5,358,892, issued Oct. 25, 1994, entitled, "An Etch Stop Useful in Avoiding Substrate Pitting with Poly Buffered LOCOS," also assigned to Micron.
Another isolation scheme is known as recessed Poly Buffered LOCOS. See for example, Shimizu, et al. "A PolyBuffer Recessed LOCOS Process for 256 Mbit DRAM Cells."
Generally, recessed PBL processes lead to two main problems. The first one is the formation of a sharp corner at the active area field edge which leads to a higher leakage under positive bias on the gate. The second problem is the formation of a groove or indentation in the shape of a ring around the active areas. This groove can later lead to the generation of a stringer around the active area after etching, thereby causing a short. For a solution to this problem see, U.S. Pat. No. 5,393,694, entitled, "Advanced Process for Recessed Poly Buffered LOCOS," also assigned to Micron.